My first Post

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Hello friends this is my first Post and its sure that you will enjoy this blog in future

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The free Library Contents

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Hi friends, While browsing the internet, I came across two great websites, and here I am putting their links:- 1). https://archive.org/ 2). http://manybooks.net/ The first website offers the digitized contents from the libraries across the world like very very old books, old video clips, some freeware soft wares from the libraries across the world. So it is very good website . The other one offers the ebooks written by very great authors like Tolstoy, Arthur Conan Doyle, and many more to download free in almost every file format(.pdf, .epub, etc...), all the ebooks published are under project Gutenberg. And finally, please donate to these websites if you can, because both of them the "archive.org" and the project Gutenberg run on donations. And Enjoy!! :-)
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How to Make Sequence Detectors(Finite State Machines)

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Hello friends, this time I came up with a new Article on how to make the State Diagrams of the Sequence Detectors-Finite State Machines(FSMs) and Sequence Detectors. Almost every Computer Science student come across the finite state machines in his/her course, some students may end up with doubts in this subject. Don't worry, in this article I will show you how to make state machines by making a simple Sequence Detector. What is in this Article:- 1).Basic Knowledge of Sequence Detection 2).How to make State Diagrams? 3).Make State table from State Diagrams and generate State Equations from these table. 4).How to design the FSMs from State Equations using Flip Flops(Here, D-Flip Flops). Let's Start:- 1).  Basic Knowledge of Sequence Detection:- The Sequence we are going to detect is the 1101 and 1001 With Overlapping. This means that suppose we are given a random binary bit string like:-                      ...
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4 bit ALU-Verilog Code

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Hi  Friends, I come up with a new post on 4 bit ALU using Verilog. It has both Structural as well as Behavioral models. This code was made by me and my friend Maunil. Our ALU has Following Components:- 1).Comparator 2).Adder/Subtractor 3).Shifter(Right/Right-Arithmetic/Left) 4).Logical Block Previously I posted an article on building 32 bit ALU in Logisim(Structural Model) This was written in verilog in Xilinx Platform and tested on Basys 2 FPGA(you may be knowing this thing and how to load our verilog code in this) So, below is the link for that code in the notepad you can make it verilog file by changing it extension to .v from .txt(You may also be knowing this. Link:- https://drive.google.com/file/d/0B36eSzxwoMyUTmRlSGxYa0RnRUk/view?usp=sharing Below is the link to .ucf file(contains the connections for basys 2 to test the code in that device) after downloading change its extension to .ucf from .txt. Link:- https://drive.google.com/file/d/0B36eSzxwoMyUcDd5V...
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